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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:17:13 11/23/2017 
-- Design Name: 
-- Module Name:    save - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity save is
    Port ( key: in std_logic;
           clr: in std_logic;
           hi1: in std_logic_vector(3 downto 0);
           hi0: in std_logic_vector(3 downto 0);
           mi1: in std_logic_vector(3 downto 0);
           mi0: in std_logic_vector(3 downto 0);
           si1: in std_logic_vector(3 downto 0);
			  si0: in std_logic_vector(3 downto 0);
           ho1: out std_logic_vector(3 downto 0);
           ho0: out std_logic_vector(3 downto 0);
           mo1: out std_logic_vector(3 downto 0);
           mo0: out std_logic_vector(3 downto 0);
           so1: out std_logic_vector(3 downto 0);
           so0: out std_logic_vector(3 downto 0));
end save;

architecture Behavioral of save is
signal cnt:integer range 0 to 6;
signal a1,a2,a3,a4,a5,a6:std_logic_vector(3 downto 0);
signal b1,b2,b3,b4,b5,b6:std_logic_vector(3 downto 0);
signal c1,c2,c3,c4,c5,c6:std_logic_vector(3 downto 0);
begin


process(clr,key,hi1,hi0,mi1,mi0,si1,si0)
begin
if clr='1' then
       cnt<=0;
       ho1<="0000";
       ho0<="0000";
       mo1<="0000";
       mo0<="0000";
       so1<="0000";
       so0<="0000";
else
if key'event and key='1' then
if cnt=6 then
  cnt<=0;
else
  cnt<=cnt+1;
end if;
end if;
end if;

case cnt is
when 0=> a1<=hi1;
a2<=hi0;
a3<=mi1;
a4<=mi0;
a5<=si1;
a6<=si0;
ho1<=hi1;
ho0<=hi0;
mo1<=mi1;
mo0<=mi0;
so1<=si1;
so0<=si0;
when 1=> b1<=hi1;
b2<=hi0;
b3<=mi1;
b4<=mi0;
b5<=si1;
b6<=si0;
ho1<=hi1;
ho0<=hi0;
mo1<=mi1;
mo0<=mi0;
so1<=si1;
so0<=si0;
when 2=> c1<=hi1;
c2<=hi0;
c3<=mi1;
c4<=mi0;
c5<=si1;
c6<=si0;
ho1<=hi1;
ho0<=hi0;
mo1<=mi1;
mo0<=mi0;
so1<=si1;
so0<=si0;
when 4=> ho1<=a1;
ho0<=a2;
mo1<=a3;
mo0<=a4;
so1<=a5;
so0<=a6;
when 5=> ho1<=b1;
ho0<=b2;
mo1<=b3;
mo0<=b4;
so1<=b5;
so0<=b6;
when 6=> ho1<=c1;
ho0<=c2;
mo1<=c3;
mo0<=c4;
so1<=c5;
so0<=c6;
when others=> ho1<=hi1;
ho0<=hi0;
mo1<=mi1;
mo0<=mi0;
so1<=si1;
so0<=si0;
end case;
end process;
end Behavioral;
